VLSI Cadence

This is my original work on VLSI Cadence Virtuoso layouts and schematics. I would like to share this and hoping will this help you in your projects. 


NOT Gate Schematic

Transient Response NOT Gate

DRC Layout for NOT Gate
NAND Gate Schematic

NAND Gate Transient Response

NOR Gate Schematic

NOR Gate Transient Response

DRAM Cell
DRAM Read Operation
DRAM Write Operation
OR Gate Pass Transistor Logic
AND Gate Pass Transistor Logic
XOR Gate Pass Transistor Logic
NAND - AND CPTL Transient Response
NOR - OR CPTL Transient Response
XOR - XNOR CPTL Transient Response
Common Source Amplifier DC Response
Common Drain Amplifier DC Response
Common Source Amplifier AC Response
Common Drain Amplifier AC Response
Differential Amplifier Schematic
Differential Amplifier AC Response
Current Mirror Schematic
Current Mirror DC Response
 Current Mirror with single side body biasing
Current Mirror with single side body biasing - DC Response
Current Mirror with both sides body biasing
Current Mirror with both sides body biasing - DC Response

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